DSP Techniques to Minimize the Bit Error Rate of Flash Memory Signals




Abstract: Data stored in Flash memory suffers from various forms of impairments. The level voltage distributions (also called Vt distributions) are not ideal. Impairments cause the level distributions to spread. This causes an increase in the raw bit error rate of the signal read from the Flash memory. In this paper, we propose signal processing techniques which optimize the signal quality read from Flash memory. The key idea is to estimate the optimal position of the read reference voltages so that the bit error rate is minimized. The problem statement is- With minimum read operations, how can we estimate the Vt distribution parameters so that the read reference can be optimally positioned to minimize the BER? Two algorithms are proposed. One is based on using the noisy observations to estimate the parameters of the cumulative distribution function. The second algorithm is based on interpolation and extrapolation of the cdf based on splines.

Bio: Ravi Motwani is currently the ECC/DSP lead for the Non-Volatile Memory Solutions Group of Intel, Santa Clara. Ravi obtained his doctoral degree from the Indian Institute of Science in 1998. He has earlier held research positions with Philips Research Labs., Netherlands, Broadcom Corporation. His current focus is on developing ECC and DSP solutions for NAND Flash Memory and emerging memory technologies. Ravi has filed 35 US patents and has 35 publications in peer reviewed conferences and journals. Ravi is the co-chair of the IEEE working group P1890 - Standard for Error Correction Coding of Flash Memory Using Low-Density Parity Check Codes.