Using Flash SSDs as Main Memory Extension with a Locality-aware Algorithm




Abstract: The potential of PCIe flash as large and slow memory behind DRAM is investigated with a locality-aware algorithm. Hierarchical data structure blocking techniques are newly applied to a stencil computation, which is one of the most typical and important computation kernels in various scientific and engineering simulations. We find a flash SSD performs satisfactorily for practical use to bridge the DRAM-Flash latency divide with the locality-aware algorithm.

Bio: Hiroko Midorikawa is an assistant professor of Seikei University in Tokyo. She joins the JST CREST project in Development of System Software Technologies for Post Peta-scale High Performance Computing. Her group interests include the Software Technology for the Deeper Memory Hierarchy in Post Peta-scale Era. She received B.S. in electrical engineering from Keio University and Ph.D. in computer science from University of Tsukuba. She worked the research laboratory of NEC more than five years.