Efficient FPGA-based Architectures of Finite Alphabet Iterative Decoders for Flash Memories




Abstract: We discuss FPGA implementations of finite alphabet iterative decoders (FAIDs) for hard-decision and 2-bit soft-decision decoding of column-weight-four LDPC codes. We present results for lengths 1KB and 2KB, and rates 0.94 and 0.91. Comparisons are made between FAIDs and offset-min-sum decoders in terms of resource usage, latency, and error-rate performance. We show that FAIDs can provide significant savings in resource usage while providing better error-floor performance than offset-min-sum.

Bio: Shiva received a Ph.D. in Electrical Engineering from the University of Arizona in Aug. 2013, and from the University of Cergy-Pontoise, France in Dec. 2012, under a dual doctoral program. His research focused on the design and analysis of low-complexity finite-precision LDPC decoders. He is currently the CEO of Codelucida LLC, a startup based in Tucson, AZ he co-founded with his former Ph.D. advisors Bane Vasic and David Declercq, that develops new low-power LDPC solutions for SSDs and HDDs.