Energy-Efficient Inclusion Properties for STT-RAM Last-Level Caches

Abstract: STT-RAM has been considered as a promising candidate for replacing conventional SRAM LLCs. However, the high write energy of STT-RAM introduces new challenges into the design of inclusion property in the cache hierarchy. In this work, we analyze the pros and cons of different existing inclusion properties. We then propose two novel policies based on the workload behavior, such as the write traffic and the data reuse between cache levels, to reduce the energy consumption of STT-RAM LLCs.

Bio: Hsiang-Yun Cheng is a Ph.D. student in the CSE Department at the Pennsylvania State University. Her advisor is Dr. Yuan Xie and she is co-advised by Dr. Mary Jane Irwin. She received her B.S. and M.S. degrees from National Taiwan University in 2007 and 2010. Her research interests focus on cache and memory management policies, with an emphasis on non-volatile memories, for multi-core systems.