Quasi-Cyclic Non-Binary LDPC Codes for MLC NAND Flash Memory




Abstract: In this work, we focus on optimizing quasi-cyclic, non-binary, low-density parity-check (QC-NB-LDPC) codes for NAND flash memory. In particular, we lower the error-floor by provably eliminating dominant absorbing sets from the graph representation of the code. We offer comparative simulation results over an accurate channel model of the threshold voltage distribution. Additionally, we present the performance/complexity trade-off in using our code.

Bio: Clayton Schoeny is a Ph.D. student in the EE department at the University of California, Los Angeles (UCLA). He received his B.S. and M.S. degrees from UCLA in 2012 and 2014, respectively. His research interests include coding for memories and interactive synchronization schemes. Schoeny has industry experience working for DIRECTV and The Aerospace Corporation.