Design a High-Performance Main Memory by Overcoming the Challenges of Crossbar Resistive Memory Architectures

Abstract: The access latency in a crossbar ReRAM array is a function of the data patterns. This combined with ReRAM's exponential relationship between its write voltage and switching latency provide opportunities for architectural optimizations. In this talk, I will first analyze microarchitectural enhancements to improve write performance. Then I will talk about an architecture-level solution which uses a simple compression based data encoding scheme to further bring down the latency.

Bio: Cong Xu recently received his Ph.D. degree in the Computer Science and Engineering Department at the Pennsylvania State University. He has a B.S. degree in microelectronics from Peking University, China in 2009. His research interest includes the modeling, architectural design, and applications of non-volatile memories. He has co-authored about 30 papers on memory system. He is also leading the development of the open source modeling tool NVSim. He is currently in the job market.