A Case for STT-RAM Based Hybrid Buffer Design for Network-on-Chip




Abstract: The breakdown of Dennard scaling prevents us from powering all transistors, leaving a large fraction of Dark Silicon. We propose to overcome the dark silicon issue with Network-on-Chip (NoC), leveraging non-volatile memory technology. In particular, we design a hybrid buffer that integrates STT-RAM with drowsy SRAM, which divides the input buffers into a hierarchy of levels operating at various power states. Experiments show 30.9% network energy saving compared with pure SRAM-based NoC design.

Bio: Jia is currently a fourth-year PhD student in Computer Engineering at University of California, Santa Barbara. He received a bachelor's degree from Harbin Institute of Technology, China, in 2011. His research interests include a broad range of computer architecture and datacenter architecture. His recent projects focus on Network-on-Chip for many-core processors, emerging non-volatile memories, and large-scale datacenter networks.