Designing a Fast and Reliable Main Memory with Memristor Technology




Abstract: In this work, we focus on Memristor technology and identify some of the significant problems in state-of-the-art implementations. These problems include sneak currents during reads and non-uniformity in cell behavior within an array. This manifests as long read latencies,long write latencies, and high cache line error rates. We provide solutions to each of these and design a system which is 12% better and has 30X lower probability of suffering a two-bit error compared to the baseline.

Bio: Manjunath Shevgoor received his B.E. from Visvesvaraya Technological University, India in 2006, and his MS from the University of Utah in 2012 in Computer Engineering. From 2006 to 2010, he worked in India as a Physical Design Engineer. He is currently pursuing a Ph.D. in Computer Engineering at the University of Utah under the guidance of Prof. Rajeev Balasubramonian. His research focuses on DRAM, Data Prefetching, Hardware Security, and Non-volatile memories including PCM and Memristors.