Compression-Expansion Coding for MLC/TLC Non-volatile Memories

Abstract: Energy and latency are two critical factors in the performance of NVM. We propose compression-expansion (CompEx) coding, a low-overhead word-level data transformation scheme that integrates 64-bit frequent pattern compression with the (3,2)8 'expansion' code for simultaneous energy and latency improvements of MLC/TLC NVM. Trace-based simulations of SPEC CPU2006 benchmarks show that CompEx coding reduces energy by 31% and latency by 28% in comparison to data-comparison write.

Bio: Poovaiah Palangappa is a PhD student at the Dept. of ECE, University of Pittsburgh. His research interests include computer architecture, networks on chip, and high-performance systems. He worked as senior design engineer at Analog Devices Inc., where he was involved in component design, design for testability, and logic built-in self-test for digital signal processors. He received his M.Tech from Indian Institute of Science, Bangalore. He is currently in the market for internships.