Admission Polices for Solid State Cache Devices

Abstract: Historically, flash endurance has not been a primary focus in cache research. In this paper, we consider admission policies for flash-based cache devices. Our goal is to improve device endurance by reducing low-value writes while maintaining cache hit rate. The paper evaluates six admission policies against several workloads. We show that some restrictive admission policies can give comparable or better hit-rates than ADMIT ALL for smaller cache sizes while greatly reducing writes to flash.

Bio: Greg Gillis received the doctoral degree in Mathematics in 1998 from the University of Arizona. Since that time he has been involved in algorithmic R&D ranging from wireless communication, video compression, and image processing, to flash-based cache devices. He now resides in Salt lake City, Utah, where he also teaches mathematics at the University of Utah and helps his better half to raise 5 children. His hobbies include hiking, body-surfing and playing the guitar.