Constructing Large and Fast Multi-Level Cell STT-MRAM based Cache for Embedded Processors




Abstract: MLC STT-MRAM has became a promising candidate as L2 cache for embedded processors. However, the long write latency limits its effectiveness. In this study we address such limitation with 2 novel designs: Line Pairing (LP) and Line Swapping (LS). LP forms fast cachelines by re-organizing MLC soft bits which are faster to write. LS dynamically stores frequently written data into these fast cachelines. Our experimental results show that LP and LS improve performance by 15% and reduce energy by 21%.

Bio: Bo Zhao is pursuing a PhD in Electrical & Computer Engineering at the University of Pittsburgh. His research interests include VLSI circuits and microarchitectures, memory systems, and modern processor architectures. Zhao has a MS from University of Pittsburgh in 2009, and a BS from Beihang University, Beijing, in 2007.