HW/SW Architecture for Speech Recognition Acceleration

Abstract: This paper describes a new hardware architecture for fast Acoustic Model scoring in embedded speech recognition systems by integrating an 8-way data-path with a NOR Flash array. This architecture localizes computation of critical algorithms and reduces decode latency and CPU load by 50% for large acoustic models, resulting in lower word error rates for natural language speech recognition.

Bio: Richard Fastow serves as the Director of Speech Technology and Algorithms at Spansion Inc. Richard attended Massachusetts Institute of Technology and Cornell University.