High-performance STT-MRAM and Its Integration for Embedded Cache Memory

Abstract: We report the current status of our spin-transfer torque magnetic RAM (STT-MRAM) development and its integration with the BEOL process for replacing conventional embedded SRAM cache memory. Our MRAM technology features a top-pinned magnetic tunnel junction (MTJ) and strain engineering for a high density memory, and a highly reliable MTJ for a cache memory. They are integrated into Cu interconnects with 300 mm facilities.

Bio: Toshihiro Sugii received the B.S., M.S., and Ph.D. degree in electrical engineering from Tokyo Institute of Technology in 1979, 1981, and 1991. In 1981, he joined Fujitsu Laboratories Ltd., Japan, where he engaged in development of VLSI devices. Since 2010, he has joined Low-power Electronics Association & Project (LEAP), Japan, where he is directing the national project on STT-MRAM. Dr. Sugii is a fellow of the Japan Society of Applied Physics and a member of the IEEE electron device society.