Low-Energy and Low-Latency Error-Correction for Phase Change Memory

Abstract: This paper proposes a novel error-correction scheme for phase change memory. Since soft errors are rare and hard errors increase gradually with the number of writes, 2-error-correcting BCH codes are integrated with error-correcting pointers (ECPs). ECPs come directly from BCH decoding results, and the verify-after-write is eliminated. Synthesis and power analysis show that the proposed scheme leads to significant overall energy and latency reductions.

Bio: Xinmiao Zhang received her Ph.D. from the University of Minnesota in 2005, and is currently an associate professor at Case Western Reserve University. Her research interests include VLSI architecture design for communications, cryptosystems, and digital signal processing. She was a recipient of the NSF CAREER Award, and the Best Paper Award at the ACM Great Lakes Symposium on VLSI. She served on many conference committees, and is currently an associate editor for TCAS-I.