Dual-Port PCM Architecture for Network Processing

Abstract: We describe a virtually pipelined memory architecture built on a dual-port phase change memory (PCM) substrate for high performance networking applications. The dual-port PCM cell significantly reduces the probability of bank conflicts due to blocking writes, delivering the large bandwidth and bank parallelism critical for such applications. Results show the dual-port PCM can reduce the expected read (write) delay by 12–40X (up to 14%) over conventional single-port PCM for 1.1-1.7X overhead.

Bio: Jiayin Li received the B.E. and M.E. degrees from Huazhong University of Science and Technology, China, in 2006 and 2008, respectively, and the Ph.D. degree in Electrical Engineering from the University of Kentucky in 2012. He is currently a post-doctoral associate in the Department of Electrical and Computer Engineering, University of Pittsburgh. His current research interests include computer architecture, software/hardware co-design, and high performance computing.