You are viewing an archived workshop website. The website for the latest workshop, NVMW 2018, can be found here

NVMW 2012


The program below is preliminary and may change before the workshop.
A printable version of the program can be found here.

Sunday, March 4

Price Center Ballroom East

System Design Issues for Solid State Storage
Steven R. Hetzler
Manager, Storage Architecture Research, IBM Fellow
1:00pm - 4:00pm

Sheraton Hotel
6:00pm - 9:00pm

Monday, March 5

Continental Breakfast
Price Center Ballroom East
8:00am - 8:45am

Opening Remarks
Price Center Ballroom East
8:45am - 9:00am

Price Center Ballroom East

Co-optimizing Systems, OS, Applications, SSDs and NVM
Richard L. Coulson
Senior Fellow, Director, Storage Technologies Group, Intel Corporation
9:00am - 10:00am

10:00am - 10:45am

Session I: Applications I
Price Center Ballroom East

Chair: Moin Qureshi

Building Storage Systems for Mobile Devices
NEC Labs∗, NEC Labs and Georgia Tech†
Nitin Agrawal∗, Hyojun Kim†, Cristian Ungureanu∗
Hathi: Durable Transactions for Memory using Flash
University of Wisconsin-Madison∗, Nou Data†, Google‡
Mohit Saxena∗, Mehul A. Shah†, Stavros Harizopoulos†, Michael M. Swift∗, Arif Merchant‡
Graph500: Traversing massive graphs with NAND Flash
Texas A&M University∗, Lawrence Livermore National Laboratory†
Roger Pearce∗, Maya Gokhale†, Nancy M. Amato∗
Enabling Application Directed Storage Devices
Princeton University∗, Fusion-io†
Anirudh Badam∗, David W. Nellans†
10:45am - 12:05pm

Lunch/Poster Session
Price Center Ballroom B
12:05pm - 1:45pm

Session II: Devices I
Price Center Ballroom East

Chair: Mircea Stan

Novel Access-Devices based on Mixed-Ionic-Electronic-Conduction (MIEC) Materials for Multi-Layer PCM and RRAM Crosspoint-Memory Arrays
IBM Almaden Research Center
Kumar Virwani, Rohit S. Shenoy, Kailash Gopalakrishnan, Geoffrey W. Burr, Charles T. Rettner, Alvaro Padilla, Don S. Bethune, Robert M. Shelby, Bryan Jackson, Bulent N. Kurdi
PreSET: Improving Read-Write Performance of Phase Change Memories by Exploiting Asymmetry in Write Times
Georgia Tech.∗, IBM TJ Watson Research Center†
Moinuddin Qureshi∗, Michele Franceschini†, Ashish Jagmohan†, Luis Lastras†
Extending Phase Change Memory Lifetime by Fine-Grained Current Regulation and Voltage Upscaling
University of Pittsburgh
Lei Jiang, Bo Zhao, Youtao Zhang, Jun Yang
Accelerating Flash Memory Access by Speculative Early Sensing Decision
Amit Berman, Yitzhak Birk
Session III: Architecture I
Price Center Ballroom A

Chair: Ted Wobber

Solid-State Cache Management
University of Wisconsin-Madison
Mohit Saxena, Michael Swift
Comparing Coordinated Garbage Collection Algorithms for Arrays of Solid-state Drives
Georgia Institute of Technology∗, Oak Ridge National Laboratory†
Junghee Lee∗, Youngjae Kim†, Sarp Oral†, Galen M. Shipman†, David A. Dillow†, Feiyi Wang†
Protecting Flash Memory SSDs against Malicious I/O Attacks
University of Nebraska-Lincoln
Lei Tian, Hong Jiang
Writeback-aware Partitioning and Replacement for Last-Level Caches in Phase Change Main Memory Systems
University of Pittsburgh
Miao Zhou, Yu Du, Bruce Childers, Rami Melhem, Daniel Mosse
1:45pm - 3:05pm

3:05pm - 3:50pm

Session IV: ECC I
Price Center Ballroom East

Chair: Etian Yaakobi

WOM Codes with History
UCSD∗, UCSD and California Institute of Technology†
Minghai Qin∗, Lele Wang∗, Eitan Yaakobi†, Young-Han Kim∗, Paul H. Siegel∗
Asymptotic Rates for Lattice-Based WOM Codes
University of Electro-Communications
Brian M. Kurkoski
Use Mutual-Information Optimized Quantization in LDPC decoding for Flash Memory
University of California, Los Angeles∗, Rensselaer Polytechnic Institute†
Jiadong Wang∗, Guiqiang Dong†, Tong Zhang†, Richard Wesel∗
A Temperature Compensated, Deep-sub-threshold Floating-gate Memory with Analog LDPC based Error-correction
Michigan State University
Ming Gu, Shantanu Chakrabartty
Session V: Applications II
Price Center Ballroom A

Chair: Simon Litsyn

SkimpyStash: Ultra-Low RAM Footprint Key-Value Store on Flash
NEC Labs∗, Microsoft Research†
Biplob Debnath∗, Sudipta Sengupta†, Jin Li†
Effective Use of Persistent Memory with Eucalyptus
IBM Research
Mohammad Banikazemi, Bulent Abali
QMDS: A Searchable File System Metadata Management Service
Lawrence Livermore National Lab∗, UC Santa Cruz†
Sasha Ames∗, Maya B. Gokhale∗, Carlos Maltzahn†
A File System for Storage Class Memory
Texas A&M University
Sheng Qiu, Xiaojian Wu, A. L. Narasimha Reddy
3:50pm - 5:10pm

5:10pm - 6:00pm

Birch Aquarium
6:00pm - 9:00pm

Tuesday, March 6

Price Center Ballroom East
8:15am - 9:00am

Price Center Ballroom East

Developments and Challenges for Next Generation Terabit Non Volatile Memories
Christophe Chevallier
NVM / Storage Division, Rambus
9:00am - 10:00am

10:00am - 10:45am

Session VI: Architecture II
Price Center Ballroom East

Chair: Peter Desnoyers

A Design for Networked Flash
Microsoft Research Silicon Valley
Ted Wobber, Mahesh Balakrishnan, Dahlia Malkhi, Vijayan Prabhakaran, John Davis, Michael Wei
Fast, Flexible Support for Transactions in a Next-Generation, Solid-State, Storage Array
University of California, San Diego
Joel Coburn, Trevor Bunker, Rajesh K. Gupta, Steven Swanson
NAND-Flash: Fast disks or Slow memory?
University of Utah∗, Princeton University†, FusionIO, Inc.‡
Kshitij Sudan∗, Anirudh Badam†, David Nellans‡
A Row Buffer Locality-Aware Caching Policy for Hybrid Memories
Carnegie Mellon University
HanBin Yoon, Justin Meza, Rachata Ausavarungnirun, Rachael Harding, Onur Mutlu
Session VII: Devices II
Price Center Ballroom A

Chair: Sudhanva Gurumurthi

Improving Write Operations in MLC Phase Change Memory
University of Pittsburgh
Lei Jiang, Bo Zhao, Youtao Zhang, Jun Yang, Bruce R. Childers
Data Mapping for Higher Performance and Energy Efficiency in Multi-Level Phase Change Memory
Carnegie Mellon University∗, HP Labs†
HanBin Yoon∗, Naveen Muralimanohar†, Justin Meza∗, Onur Mutlu∗, Norman P. Jouppi†
Multi Nonvolatility Level STT-RAM Cache Hierarchy
Polytechnic Institute of New York University∗, National University of Singapore†, Qualcomm Incorporated‡
Zhenyu Sun∗, Xiuyuan Bi∗, Hai Li∗, Weng-Fai Wong†, Wenqing Wu‡, Xiaochun Zhu‡
A RRAM-based Memory System and Applications
Polytechnic Institute of NYU∗, Nanyang Technological University†, Air Force Research Laboratory‡
Yi-Chung Chen∗, Hai Li∗, Wei Zhang†, Robinson E. Pino‡
10:45am - 12:05pm

Lunch/Poster Session
Price Center Ballroom East
12:05pm - 1:15pm

Session VIII: ECC II
Price Center Ballroom East

Chair: Lara Dolocek

Half-Wits: Software Techniques for Low-Voltage Probabilistic Storage on Microcontrollers with NOR Flash Memory
University of Massachusetts Amherst∗, Texas A&M University†
Mastooreh Salajegheh∗, Yue Wang†, Erik Learned-Miller∗, Anxiao (Andrew) Jiang†, Kevin Fu∗
Tackling Intracell Variability in TLC Flash Through Tensor Product Codes
Ryan Gabrys∗, Eitan Yaakobi†, Laura Grupp†, Steve Swanson†, Lara Dolecek∗
Channel Modeling and Information Theoretic Characterization for Spin-Torque Transfer Magnetic Random Access Memory (STT-MRAM)
Data Storage Institute, Singapore
Cai Kui, Qin Zhiliang, Rachid Sbiaa, Meng Hao, Chen Bingjin
Gradual Error Correction Code to Extend the Lifetime of Flash Memory
Chanha Kim
Practical Re-Write Codes with Access Considerations
Technion Israel Institute of Technology∗, California Institute of Technology, University of California, San Diego†
Yuval Cassuto∗, Eitan Yaakobi†
1:15pm - 2:35pm

2:35pm - 3:00pm

Stuart Collection
3:00pm - 4:30pm