Non-volatile Memories Workshop 2010

April 11-13, 2010

Non-volatile Memories Workshop 2010

Sunday, April 11
2:00pm-5:00pm	Sunday PM Tutorial Session CMRR Auditorium
	Khaled Amer SNIA/SSSI	Solid-State Storage Overview
6:00pm	Reception - Estancia Hotel La Jolla
Monday, April 12
8:00am	Continental Breakfast Calit2 - Atkinson Hall
8:30am	Morning Session Calit2 - Atkinson Hall	Device Technologies
8:30	Cuong Trinh SanDisk	A 7.8MB/s 64Gb 4-Bit/Cell NAND Flash Memory on 43nm CMOS Technology
8:50	Greg Atwood Numonyx	Phase Change Memory: Development Progress and System Opportunities
9:10	Geoffrey Burr IBM	Storage Class Memory
9:30	Nick Rizzo Everspin	Toggle and Spin Torque: MRAM at Everspin Technologies
9:50am	Break
10:10	Alexander Driskill-Smith Grandis	Latest Advances and Future Prospects of STT-RAM
10:30	Xiaobin Wang Seagate	From Spin Torque Random Access Memory to Spintronic Memristor
10:50	Janice Nickel HP	Memristor RRAM: Materials and Mechanisms
11:10am	Break
11:30am	Morning Session (cont.)	Channel Modeling and Coding
11:30	Laura Grupp UCSD	Characterizing Flash Memory: Anomalies, Observations, and Applications
11:50	Eitan Yaakobi UCSD	Coding for Flash Memories
12:10pm	Xinmiao Zhang Case Western	Error Correction for Multilevel NAND Flash Memory Using Reed-Solomon Codes
12:30pm	Luncheon Calit2
1:50pm	Afternoon Se ssion Calit2 - Atkinson Hall	Channel Modeling and Coding (cont.)
1:50	Zhiying Wang Caltech	Variations of Rank Modulation for Flash Memories
2:10	Andrew Jiang Texas A & M	Emerging Coding Techniques for Flash Memories
2:30	Luis Lastras Montano IBM (Watson)	Towards an Information and Coding Theory for Non-volatile Memories
2:50	Michele Franceschini IBM (Watson)	Architectural Solutions for Storage-Class Memory in Main Memory
3:10pm	Break
3:30pm	Afternoon Session (cont.)	System Architecture (Part 1)
3:30	Bhuvan Urgaonkar Penn State	DFTL: A Flash Translation Layer Employing Demand-based Selective Caching of Page-level Address Mappings (talk cancelled)
3:50	John Davis Microsoft	A Survey of NVM Research at MSR SVC
4:10	David Andersen CMU	System and Algorithmic Adaptation for Flash
4:30pm	Break
4:50	Allan Snavely SDSC, UCSD	Gordon: An Architecture for Data Intensive Computing
5:10	Ed Nightingale Microsoft	Better I/O Through Byte-Addressable, Persistent Memory
5:30pm	Adjourn Afternoon Session
7:00pm	Dinner Estancia Hotel La Jolla
8:00pm	After-Dinner Panel	Directions for NVM Research
	Geoffrey Burr IBM	PCM Technology/Storage Class Memory (SCM)
	Simon Litsyn SanDisk/Tel-Aviv Univ.	Coding
	John Davis Microsoft	Flash SSD Architecture
	Ed Nightingale Microsoft	Non-flash Architecture
	Allan Snavely SDSC, UCSD	Applications
	Roger Bohn GIIC, UCSD	How Much Information
Tuesday, April 13
8:00am	Continental Breakfast Calit2 - Atkinson Hall
8:30am	Morning Session Calit2 - Atkinson Hall	System Architecture (Part 2)
8:30	Joel Coburn UCSD	Non-volatile Transactional Memory
8:50	Engin Ipek Univ. Rochester	Dynamically Replicated Memory: Building Reliable Systems from Nanoscale Resistive Memories
9:10	David Flynn Fusion-io	Introduction to Fusion-io's NAND Flash Memory Tier
9:30am	Break
9:50	Morning Session (cont.)	Applications of Non-volatile Memories
9:50	Brett Kettering LANL	The Role of NVM from an Application Perspective
10:10	Scott Stetzer STEC	Enterprise Solid State Drives and Defining Characteristics of Enterprise Storage
10:30	Rajesh Gupta UCSD	A System-Level Perspective on Adaptive and Integrated Memory Systems
10:50	Yanlei Diao Univ. Mass.	Lazy-Adaptive Tree: An Optimized Index Structure for Flash Devices
11:10am	Break
11:30	Seung H. Kang Qualcomm	Embedded STT-MRAM for Mobile System-on-Chips
11:50	Nicholas Schork The Scripps Research Institute	Large-scale Gene Discovery and Association Studies
12:10	Al Borchers Google	Google's Experiences with Flash Memory (viewgraphs not available)
12:30pm	Workshop Conclusion
12:30pm	Luncheon Calit2
2:00pm	Tour	Calit2 Technology Laboratories